CHIP GALLERY

AUDIO ANALOG FEATURE EXTRACTOR BASED ON TIME-MODE ANALOG SIGNAL PROCESSING (65NM LP CMOS)
[VLSI22]

TWIN PI AND DELTA QDLL FOR WIDEBAND SERIAL-LINK CLOCKING (65NM CMOS) 
[ISSCC22, JSSC22]

QDLL AND MPIL-ROSC FOR HIGH-ACCURACY, LOW-JITTER MULTI-PHASE CLOCKING (65NM CMOS) 
[ISSCC21, JSSC22]

SELF-DUTY CYCLED, SELF-SYNCHRONIZED UWB RECEIVER SOC (65NM CMOS) 
[ISSCC13]

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CURRENT REFERENCE PRE-CHARGED ZERO-CROSSING PIPELINE-SAR ADC (65NM CMOS) 
[CICC12]

UWB RECEIVER WITH AUTOMATIC THRESHOLD RECOVERY (65NM CMOS) 
[RFIC12]

PHASE LOCKED LOOP
(65NM CMOS) 
[CICC11]

ZERO-CROSSING BASED PIPELINED ADC
(65NM CMOS) 

WAKE-UP RECEIVER USING ULTRASOUND DATA COMMUNICATIONS
(65NM CMOS) 
[VLSI11, JSSC13]

CURRENT-CHARGE-PUMP PIPELINED ADC
(90NM CMOS) 
[TCASII11]

CMOS PHASE SHIFTER WITH FREQUENCY DOUBLING FOR MULTIPLE-ANTENNA TRANSCEIVER SYSTEMS 
(90NM CMOS) 
[RWW11]

0.6V 900MHZ RECEIVER WITH INTERFERENCE CANCELLATION
(65NM CMOS) 
[VLSI10, JSSC11]

DIRECT CONVERSION FRONT END WITH DIGITALLY ASSISTED IIP2 BACKGROUND SELF CALIBRATION
(130NM CMOS) 
[ISSCC10, JSSC11]

IR-UWB TRANSCEIVER CHIPSET USING SELF-SYNCHRONIZING OOK MODULATION 
(90NM CMOS) 
[ISSCC10, JSSC11]

A SINGLE-CHIP 0.125-32GHZ SIGNAL SOURCE 
(180NM SIGE BICMOS) 
[RFIC08] AND [JSSC11] (modified version)

A 0.042-MM2 FULLY INTEGRATED ANALOG PLL WITH STACKED CAPACITOR-INDUCTOR 
(45NM CMOS) 
[ESSCIRC08]

VOLTAGE REFERENCE FOR ULTRA LOW VOLTAGE SUPPLY OPERATION 
(90NM CMOS) 
[CICC08]

​UWB PULSE RADIO RECEIVER 
(90NM CMOS) 
[RFIC08, JSSC09]

UWB PULSE RADIO TRANSMITTER 
(90NM CMOS) 
[RFIC08, JSSC09]

HIGH PERFORMANCE 2GHZ DIRECT CONVERSION FRONT END 
(130NM CMOS) 
[RFIC08, JSSC09]

​0.6V HIGHLY INTEGRATED 2.4GHZ RECEIVER AND SYNTHESIZER 
(90NM CMOS) 
[ISSCC08, 2010]

2.6GHZ INDUCTIVE POWER DELIVERY FOR CONTACTLESS TEST 
(90NM CMOS) 
[ICMTS08]

RING OSCILLATOR MISMATCH TEST STRUCTURE 
(0.25 UM/40 GHZ BICMOS) 
[CICC07]

0.5V 8BIT 10MSPS PIPELINED ADC 
(90NM CMOS) 
[VLSI07, JSSC08]

0.5V 2.4GHZ SLIDING-IF RECEIVER 
(90NM CMOS) 
[RFIC07, JSSC08]

0.65/0.5V FREQUENCY SYNTHESIZER 
(90NM CMOS) 
[ISSCC07]

QUADRATURE VCO WITH CAPACITIVE COMMON-SOURCE COUPLING
(0.25 UM/40 GHZ BICMOS) 
[ESSCIRC06]

0.5 V TRACK AND HOLD AMPLIFIER 
(0.25UM CMOS) 
[VLSI06, JSSC07]

0.5 V 900MHZ RF FRONT-END 
(0.18UM CMOS) 
[VLSI06]

​5-BIT DAC FOR UWB PULSE GENERATION 
(0.25 UM/40 GHZ FT BICMOS) 
[ISCAS06]

​0.5 V SIGMA DELTA CONVERTER 
(0.18UM CMOS) 
[ISSCC06, JSSC07]

VCO WITHOUT (VCO1) AND WITH (VCO2) TAIL CURRENT SHAPING
(0.25 UM/40 GHZ BICMOS) 
[CICC05, JSSC06]

​VCO IN A COIL 
(0.25 UM/40 GHZ BICMOS) 
[CICC05, JSSC06]

DISTRIBUTED CMOS LNA FOR UWB APPLICATIONS 
(0.18UM CMOS) 
[VLSI05, JSSC06]

0.5 V FILTER WITH PLL-BASED TUNING 
(0.18UM CMOS) 
[ISSCC05, JSSC05]

0.5 V BULK-INPUT AMPLIFIER 
(0.18UM CMOS) 
[ESSCIRC04, JSSC05]

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